module test(
	input	a,
	input	b,
	input	c,
	input	clk,
	input	rstn
);
	wire	d;
	reg	[1:0] save[1:0];
	integer i;
	
	always @(posedge clk or negedge rstn) begin
		if(!rstn)begin
			for(i=0;i<2;i=i+1) begin
				save[i] <= 0;
			end
		end
		else begin
			save[c] <= {a,b};
		end
	end
	assign d = save[1][0];

endmodule